During the fabrication of integrated circuits such as memory devices, it is conventional to test such integrated circuits at several stages during the fabrication process. For example, the integrated circuits are normally connected to a tester with a probe card when the integrated circuits are still in wafer form. In a final test occurring after the integrated circuits have been diced from the wafer and packaged, the integrated circuits are placed into sockets on a load board. The load board is then placed on a test head, typically by a robotic handler. The test head makes electrical contact with conductors on the load board that are connected to the integrated circuits. The test head is connected through a cable to a high-speed tester so that the tester can apply signals to and receive signals from the integrated circuits.
While the above-described testing environment works well in many applications, it is not without its limitations and disadvantages. For example, it is very difficult to test various timing characteristics of the integrated circuits, particularly at the high operating speeds for which such integrated circuits are designed. This difficulty in testing timing characteristics results primarily from the propagation delays in the cable coupling the tester to the test head. The cables that are typically used in such testing environments are often fairly long, thus making the delays of signals coupled to and from the integrated circuits correspondingly long and often difficult to predict.
Another problem with the above-described testing environment is that it may not accurately simulate the conditions in which the integrated circuits will be actually used. In actual use, integrated circuits, such as dynamic random access memory (“DRAM”) devices are typically mounted on a printed circuit board. Signals are applied to the integrated circuits by other integrated circuits mounted on the board, and signals generated by the integrated circuits are received by other integrated circuits mounted on the board. In most applications, signals are not coupled to and from the integrated circuits through long cables coupled to distant electronic devices. Therefore, the testing environment is normally quite different from the environment in which the integrated circuits will operate in normal use.
While techniques have been developed to deal with these difficulties, the use of these techniques results in testers that are highly complex and often very expensive. A large number of testers are normally required for a high capacity semiconductor fabrication plant, thus greatly increasing the cost of the plant and the expense of testing the integrated circuits.
One improved testing system that has been proposed is to fabricate an integrated test circuit that performs most if not all of the functions of conventional testers, and mount the integrated test circuit on the test head or load board to which the integrated circuits being tested are coupled. By placing the testing function on the test head or load board itself, the problems inherent in coupling test signals between a testing system and a test head are eliminated. As a result, the circuits can be tested in a more realistic environment. Furthermore, since even custom integrated circuits can be fabricated relatively inexpensively, the cost of testing systems can be greatly reduced.
One difficulty in using an integrated test circuit in this manner stems from the difficulty in accurately testing timing margins of memory devices. For example, synchronous memory devices normally receive a write data strobe signal, which is commonly abbreviated as “DQS.” A typical DQS signal 2 is shown in FIG. 1. The DQS signal 2 includes an active portion 4 containing several logic level transitions, which are synchronized to write data signals that are also applied to the memory devices. The active portion 4 of the DQS signal 2 is preceded by a preamble 6, and it is followed by a postamble 8. In the example shown in FIG. 1, the active portion 4 includes two falling edge transitions and three rising edge transitions, the first of which terminates the preamble 6 and the last of which initiates the postamble 8.
Specifications for synchronous memory devices normally specify a range of acceptable timing values for the DQS preamble 6 and postamble 8. It is important to ensure that a memory device being tested meets these specifications. The ability of a memory device to meet the preamble and postamble width specifications is normally tested by applying DQS signals to the memory device having preambles and postambles that span the range of acceptable values. The ability of the memory device to operate properly with all of the preambles and postambles in the specified range is then determined by reading data from the memory device that have been written using DQS signals with the various preamble and postamble values.
Unfortunately, with modern high-speed memory devices, it is difficult to generate test signals that have precise but very small time durations, such as preambles and postambles. Expensive high-speed testers of the type normally used to test memory devices are capable of precisely controlling the timing of each transition of the DQS signal, including the preambles and postambles. However, the lack of a good timing mechanism that can easily be fabricated in an integrated circuit threatens to preclude the use of an integrated test circuit mounted on a load board or test head from accurately testing whether a memory device meets preamble and postamble specifications.
There is therefore a need for a testing system and method that can be easily fabricated in an integrated circuit to allow an integrated test circuit mounted on a load board, test head or the like to generate DQS signals having preambles and postambles with very precisely controlled durations.